| ADS8323与高速FIFO接口电路的CPLD实现 |
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| 引用本文： | 倪冬,钟波. ADS8323与高速FIFO接口电路的CPLD实现[J]. 微计算机信息, 2007, 23(20): 174-175 |
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| 作者姓名： | 倪冬 钟波 |
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| 作者单位： | 1. 476009,洛阳,空军驻洛阳地区军事代表室
2. 100081,北京,北京航空航天大学仪器科学与光电工程学院 |
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| 摘 要： | 以CPLD为逻辑控制核心实现了ADS8323与高速FIFO的接口电路,该电路具有可靠性高、通用性强、易于移植等特点。在设计过程中,以QuartusII作为开发环境,采用图形输入和VerilogHDL语言输入相结合的方式,简化了开发流程。
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| 关 键 词： | 高速FIFO 接口电路 QuartusⅡ |
| 文章编号： | 1008-0570（2007）07-2-0174-02 |
| 修稿时间： | 2007-05-23 |
Implementation of Interface between ADS8323 and FIFO Based on CPLD |
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| NI DONG,ZHONG BO. Implementation of Interface between ADS8323 and FIFO Based on CPLD[J]. Control & Automation, 2007, 23(20): 174-175 |
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| Authors: | NI DONG ZHONG BO |
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| Affiliation: | NI DONG ZHONG BO |
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| Abstract: | The interface between ADS8323 and high-speed FIFO is designed and implemented by CPLD in the paper. The interface circuit has the features of high-reliability, strong-generalization, easy-migration and so on. With the QuartusII integration develop-ment environment, using both graphic and Verilog HDL makes design easier. |
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| Keywords: | ADS8323 CPLD |
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