| 2.5Gb/s 0.18μm CMOS时钟数据恢复电路 |
| |
| 引用本文： | 刘永旺,王志功,李伟.2.5Gb/s 0.18μm CMOS时钟数据恢复电路[J].半导体学报,2007,28(4). |
| |
| 作者姓名： | 刘永旺 王志功 李伟 |
| |
| 作者单位： | 东南大学射频与光电集成电路研究所,南京,210096 |
| |
| 摘 要： | 采用TSMC公司标准的0.18μm CMOS工艺,设计并实现了一个全集成的2.5Gb/s时钟数据恢复电路.时钟恢复由一个锁相环实现.通过使用一个动态的鉴频鉴相器,优化了相位噪声性能.恢复出2.5GHz时钟信号的均方抖动为2.4ps,单边带相位噪声在10kHz频偏处为-111dBc/Hz.恢复出2.5Gb/s数据的均方抖动为3.3ps.芯片的功耗仅为120mW.
|
| 关 键 词： | 时钟恢复 数据恢复 锁相环 动态鉴频鉴相器 |
2.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit |
| |
| Liu Yongwang,Wang Zhigong,Li Wei.2.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit[J].Chinese Journal of Semiconductors,2007,28(4). |
| |
| Authors: | Liu Yongwang Wang Zhigong Li Wei |
| |
| Abstract: | A 2.5Gb/s clock and data recovery (CDR) circuit is designed and realized in TSMC's standard 0.18μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization, a dynamic phase and frequency detector (PFD) is used in the PLL. The rms jitter of the recovered 2. 5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW. |
| |
| Keywords: | clock recovery data recovery phase locked loop dynamic phase and frequency detector |
| 本文献已被 万方数据 等数据库收录！ |
| 点击此处可从《半导体学报》浏览原始摘要信息 |
|
点击此处可从《半导体学报》下载全文 |
