一种简易的UART IP核的设计与实现

文章主要介绍一种简易通用的UART IP核的设计。UART作为一种短距离、低成本通信的串行传输接口,随着嵌入式系统的迅速发展,已成为SoC(System on Chip)芯片中的一个重要部件,在数字通信中得到了广泛的应用。本设计在对UART的串行通信协议进行详细分析的基础上,采用Verilog HDL语言对ALTERA的Cyclone系列FPGA进行设计,用一片FPGA实现了UART的发送、接收和波特率发生等功能,并验证了结果。这种灵活的设计方法使整体设计紧凑、小巧,提高了系统的兼容性,节约了硬件成本,具有较强的推广价值。

Design and Implementation of a Simple UART IP Core

This paper presents a design of a simple UART IP core. UART is a short-distance and low-cost serial communication interface that is applied widely in digital communication, and UART IP core becomes an important component of SOC, as the fast development of embedded system. This paper introduces the method of designing UART IP core with FPGA chip. It analyses the protocol of serial communication, and then the UART IP core is implemented on EP1C6Q240C8 with Verilog HDL, which realizes all needed function such as transmitter, receiver, baud rate generator and so on with only one FPGA chip. This flexible design quickens the speed of data process, improves the system compatibility, saves the expense of the hardware and is popularity.