| 一种降低VDMOS导通电阻的新结构研究 |
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| 引用本文： | 杨永晖,唐昭焕,张正元,刘勇,王志宽,谭开洲,冯志成.一种降低VDMOS导通电阻的新结构研究[J].半导体学报,2011,32(2):024005-4. |
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| 作者姓名： | 杨永晖 唐昭焕 张正元 刘勇 王志宽 谭开洲 冯志成 |
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| 作者单位： | 中国电子科技集团公司第二十四研究所,中国电子科技集团公司第二十四研究所 |
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| 摘 要： | 本文提出了一种降低VDMOS导通电阻的新结构，从理论上分析了该结构在保证VDMOS器件击穿电压保持不变的前提下，可以降低VDMOS的比导通电阻约22%，同时该新结构仅需要在原VDMOS器件版图的基础上增加一个埋层，工艺可加工性较强。把该结构用于一款200V耐压的N沟道VDMOS器件的仿真分析，器件元胞的比导通电阻降低了23%，采用三次外延四次埋层的制作方式，器件的比导通电阻可以降低33%，该新结构在条栅VDMOS研制方面具有广阔的应用前景。
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| 关 键 词： | VDMOS器件 器件结构 低导通电阻 CAD工具 击穿电压 结构处理 电阻值 N沟道 |
| 收稿时间： | 8/4/2010 11:20:04 AM |
A novel structure in reducing the on-resistance of a VDMOS |
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| Yang Yonghui,Tang Zhaohuan,Zhang Zhengyuan,Liu Yong,Wang Zhikuan,Tan Kaizhou and Feng Zhicheng.A novel structure in reducing the on-resistance of a VDMOS[J].Chinese Journal of Semiconductors,2011,32(2):024005-4. |
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| Authors: | Yang Yonghui Tang Zhaohuan Zhang Zhengyuan Liu Yong Wang Zhikuan Tan Kaizhou and Feng Zhicheng |
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| Affiliation: | Sichuan Institute of Solid-State Circuits, CETC, Chongqing 400060, China; National Laboratory of Analog ICs, Chongqing 400060, China;Sichuan Institute of Solid-State Circuits, CETC, Chongqing 400060, China;Sichuan Institute of Solid-State Circuits, CETC, Chongqing 400060, China; National Laboratory of Analog ICs, Chongqing 400060, China;Sichuan Institute of Solid-State Circuits, CETC, Chongqing 400060, China; National Laboratory of Analog ICs, Chongqing 400060, China;Sichuan Institute of Solid-State Circuits, CETC, Chongqing 400060, China;Sichuan Institute of Solid-State Circuits, CETC, Chongqing 400060, China; National Laboratory of Analog ICs, Chongqing 400060, China;Sichuan Institute of Solid-State Circuits, CETC, Chongqing 400060, China |
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| Abstract: | A novel structure of a VDMOS in reducing on-resistance is proposed. With this structure, the specific on-resistance value of the VDMOS is reduced by 22% of that of the traditional VDMOS structure as the breakdown voltage maintained the same value in theory, and there is only one additional mask in processing the new structure VDMOS, which is easily fabricated. With the TCAD tool, one 200 V N-channel VDMOS with the new structure is analyzed, and simulated results show that a specific on-resistance value will reduce by 23%, and the value by 33% will be realized when the device is fabricated in three epitaxies and four buried layers. The novel structure can be widely used in the strip-gate VDMOS area. |
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| Keywords: | VDMOS on-resistance specific on-resistance breakdown voltage epitaxial layer resistance |
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