CdZnTe graded buffer layers for HgCdTe/Si integration |
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Authors: | M. E. Groenert J. K. Markunas |
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Affiliation: | (1) U.S. Army RDECOM CERDEC NVESD, 10221 Burbeck Rd., 22060 Ft. Belvoir, VA |
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Abstract: | To investigate the potential benefits of compositional grading for dislocation control in CdTe/Si growth, Cd1−xZnxTe buffer layers with x graded smoothly from 1 to 0 have been deposited on Si (211) surfaces. Growth has been characterized using reflection high-energy electron diffraction (RHEED), x-ray diffraction (XRD), and etch pit density measurements. XRD showed an increase in rocking curve full-width at half-maximum (FWHM) and global lattice tilt with decreasing x values. Tilt was also observed to increase as buffer growth temperature was increased. Final surface dislocation densities did not decrease below 7×106 cm−2. EPD surface dislocation measurements showed reduced dislocation densities and dislocation clustering along the and lines for CdTe cap layers grown on partially graded Cd1−xZnxTe buffer layers with slow compositional grading rates. Samples grown with faster grading rates showed higher final EPD values, with dislocations clustering along the and lines. |
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Keywords: | CdZnTe CdTe/Si dislocations tilt graded buffer Z |
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