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SoC设计中的低功耗策略
引用本文:张富彬, HO Ching-Yen, 彭思龙,. SoC设计中的低功耗策略[J]. 电子器件, 2007, 30(2): 633-637
作者姓名:张富彬   HO Ching-Yen   彭思龙  
作者单位:1. 中国科学院自动化研究所,国家专用集成电路设计工程研究中心,北京,100080
2. Synopsys Inc.Mountain View CA 94043
摘    要:低功耗设计已经成为片上系统(SoC)设计的主题.当今的设计已经从过去的性能、面积二维目标转变为性能、面积和功耗的三维目标.本文深入探讨了片上系统设计中的低功耗设计策略,在晶体管和逻辑门级、寄存器传输级和系统结构级各设计抽象层次上阐述了低功耗设计所面临的问题,并给出了各级的低功耗优化策略.

关 键 词:低功耗  片上系统  静态功耗  动态功耗  动态功耗管理
文章编号:1005-9490(2007)02-0633-05
修稿时间:2006-01-11

Low Power Strategy in SoC Design
ZHANG Fu-bin,HO Ching-Yen,PENG Si-long. Low Power Strategy in SoC Design[J]. Journal of Electron Devices, 2007, 30(2): 633-637
Authors:ZHANG Fu-bin  HO Ching-Yen  PENG Si-long
Affiliation:National ASIC Design Engineering Center,Institute of Automation,Chinese Academy of Science,Beijing 100080,China;2.Synopsys Inc.Mountain View CA 94043
Abstract:Low power has emerged as a principal theme in today's SoC design.Power has became as important as performance and area in SoC design.This paper presents an in-depth discussion of low power design strategies in SoC design and describes the many issues facing designers at transistor and gate,RTL and system levels of design abstraction.Finally it provides all kings of low power design strategies at every abstraction levels.
Keywords:low power  SoC  static power  dynamic power  dynamic power manager
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