VLSI片上互连线电感提取技术及考虑电感效应的互连分析

VDSM工艺下，芯片的高速、高集成度趋使电磁耦合作用不容忽略；而电感效应的引入使VLSI设计和验证变得复杂，本文阐述了VLSI片上互连线电感提取技术现状及发展方向，对各类提取方法作了扼要比较；同时探讨了互连分析中包含电感效应时存在的部分问题和解决办法，以期作为提高VLSI设计、分析和验证效率的有效向导。

Parasitic Inductance Modeling for On-chip Interconnects Based on IC Analysis on Inductive Effects

Since VDSM designs tend to be much faster and denser, inductive effects is of VLSI interconnects are becoming more and more important. While parasitic inductance is taken into account, most IC design and verification methodologies are significantly complicated. In this tutorial paper we reviewed recent developments in inductance extraction for on-chip interconnects, and discussed some resulting analysis and verification problems. A subset of recent results for partially addressing the challenge was presented. We hope that the paper will be a good guidance for VLSI design, analysis and verification.