Micropower CMOS S&H circuit for ambient intelligence applications |
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| Authors: | Lopez-Martin AJ De La Cruz CA Ugalde X Carvajal RG Ramirez-Angulo J |
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| Affiliation: | Dept. of Electr. & Electron. Eng., Public Univ. of Navarra, Pamplona, Spain; |
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| Abstract: | A novel sample and hold (S&H) circuit is presented based on the use of a class AB CMOS operational transconductance amplifier with very high slew rate and very low static power consumption. The circuit has been fabricated in a 0.5 /spl mu/m double-poly CMOS technology. The quiescent power consumption is only 80 /spl mu/W using a dual supply voltage of /spl plusmn/1.35 V. The S&H occupies 0.075 mm/sup 2/ of silicon area. |
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