首页 | 本学科首页   官方微博 | 高级检索  
     


Convex regularization-based hardware/software co-design for real-time enhancement of remote sensing imagery
Authors:Alejandro Castillo Atoche  Y. Shkvarko  D. Torres Roman  H. Perez Meana
Affiliation:(1) CINVESTAV del IPN, Unidad Guadalajara, Avenida Científica #1145, Colonia El Bajío, CP 45015 Zapopan, Jalisco, Mexico;(2) Universidad Autónoma de Yucatán, Av. Industrias No Contaminantes s/n, Apdo. Postal 150, Mérida, Yucatán, Mexico;(3) ESIME del IPN, Unidad Culhuacan, Av. Santa Ana #1000, Col. San Fco. Culhuacan, Del. Coyoacan, Mexico DF, Mexico
Abstract:In this paper, we address a new approach for high-resolution reconstruction and enhancement of remote sensing (RS) imagery in near-real computational time based on the aggregated hardware/software (HW/SW) co-design paradigm. The software design is aimed at the algorithmic-level decrease of the computational load of the large-scale RS image enhancement tasks via incorporating into the fixed-point iterative reconstruction/enhancement procedures the convex convergence enforcement regularization by constructing the proper projectors onto convex sets (POCS) in the solution domain. The established POCS-regularized iterative techniques are performed separately along the range and azimuth directions over the RS scene frame making an optimal use of the sparseness properties of the employed sensor system modulation format. The hardware design is oriented on employing the Xilinx Field Programmable Gate Array XC4VSX35-10ff668 and performing the image enhancement/reconstruction tasks in a computationally efficient parallel fashion that meets the near-real time imaging system requirements. Finally, we report some simulation results and discuss the implementation performance issues related to enhancement of the real-world RS imagery indicative of the significantly increased performance efficiency gained with the developed approach.
Contact Information D. Torres Roman
Keywords:Remote sensing imagery  Convex regularization  Synthetic aperture radar  Hardware/software co-design  FPGA
本文献已被 SpringerLink 等数据库收录!
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号