Disposable polysilicon LDD spacer technology |
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Authors: | Parrillo LC Pfiester JR Lin J-H Travis EO Sivan RD Gunderson CD |
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Affiliation: | Motorola Inc., Austin, TX; |
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Abstract: | An advanced 0.5-μm CMOS disposable lightly doped drain (LDD) spacer technology has been developed. This 0.5-μm CMOS technology features surface-channel LDD NMOS and PMOS devices, n+/p+ poly gates, 125-A-thick gate oxide, and Ti-salicided source/drain/gate regions. Using only two masking steps, the NMOS and PMOS LDD spacers are defined separately to provide deep arsenic n+ regions for lower salicided junction leakage, while simultaneously providing shallow phosphorus n- and boron p- regions for improved device short-channel effects. Additionally, the process allows independent adjustment of the LDD and salicide spacers to optimize the LDD design while avoiding salicide bridging of source/drain to gate regions. The results indicate extrapolated DC hot-carrier lifetimes in excess of 10 years for a 0.3-μm electrical channel-length NMOS device operated at a power-supply voltage of 3.3 V |
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