| 一款高端数字SOC设计的系统级验证 |
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| 引用本文： | 杜敏,王世明.一款高端数字SOC设计的系统级验证[J].计算机工程,2005,31(21):198-200. |
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| 作者姓名： | 杜敏 王世明 |
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| 作者单位： | 上海交通大学电子工程系,上海,200030 |
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| 摘 要： | 集成电路行业的发展，为SOC没计积累了丰富的IP库和设计方法。采用系统没计常用的基于平台的方法，可以快速完成系统的集成。但要完成对整个系统的验证，可能要占到整个设计周期70％以上的时问。而验证的方法是具有多样性的。该文以一款高端SOC的没计经历，简单描述了系统级验证过程，并以同步串联接口模块为例详细介绍了在系统级对RTL和门级网表的验证，以及验证所采用的特殊方法。
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| 关 键 词： | SOC 系统验证 IP 验证环境 |
| 文章编号： | 1000-3428（2005）21-0198-03 |
| 收稿时间： | 2004-09-23 |
| 修稿时间： | 2004-09-23 |
System-level Verification of a High-end Digital SOC Design |
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| DU Min,WANG Shiming.System-level Verification of a High-end Digital SOC Design[J].Computer Engineering,2005,31(21):198-200. |
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| Authors: | DU Min WANG Shiming |
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| Affiliation: | Electronic Engineering Department. Shanghai Jiaotong University, Shanghai 200030 |
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| Abstract: | With the development of lC industry, there are many lPs and methodologies available for SOC design. Using platform-based design, a SOC can be integrated rapidly. But the whole verification process may need 70% design effort. There are many ways to verify the SOC, and every way has its own advantage. This paper based on experience of a SOC design describes the verification process of system level and a special method when no simulation model available. |
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| Keywords: | SOC System-level verification IP Verification environment |
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