基于FPGA的高速流水定点乘法器的设计

目前,多数定点高速乘法器的速度都在百兆以下。在比较各种定点乘法器的基础上,提出了一种基于Xilinx的Virtex FPGA系列器件的快速流水定点乘法器的实现方法,可将乘法速度提高至150MHz以上,大大提高了运算速度。文中以24×24位乘法器为例,给出了VHDL代码与综合仿真布线结果。此乘法器已应用于工程实践中,并且收到了良好的效果。

Design of High Speed Pipeline Fixed - point Multiplier Based on FPGA

At the present time the speed of most high speed multiplier is below 100MHz.Comparing with other multipliers,have put forward a method of realizing high speed multiplier based on Xilinx Virtex FPGA apparatus which could improve the speed to 150MHz.Have list the VHDL code for the exemple of 24x24 bit multiplier and the result of systhesis in the text.The multiplier designed has been used in project and the effect is quite nice.