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基于VHDL故障注入的处理器敏感性分析
引用本文:武振平,付方发,肖立伊. 基于VHDL故障注入的处理器敏感性分析[J]. 微电子学与计算机, 2012, 29(10): 51-54,59
作者姓名:武振平  付方发  肖立伊
作者单位:哈尔滨工业大学微电子中心,黑龙江哈尔滨,150001
基金项目:哈尔滨市科技创新人才研究专项基金(2012RFXXG042)
摘    要:针对航天应用的处理器敏感性评估需求,采用仿真命令技术开发了一种基于VHDL的故障注入工具.以LEON3处理器为目标模型进行了故障注入实验,得到了流水线寄存器的敏感性,并对敏感性较高的寄存器加固之后再次进行可靠性评估,从而验证了该故障注入工具的有效性.本故障注入工具适用于基于VHDL的RTL级处理器的软错误敏感性分析.

关 键 词:故障注入  敏感性分析  仿真命令  VHDL

Sensitivity Analysis for Processor Based on VHDL Fault Injection
WU Zhen-ping,FU Fang-fa,XIAO Li-yi. Sensitivity Analysis for Processor Based on VHDL Fault Injection[J]. Microelectronics & Computer, 2012, 29(10): 51-54,59
Authors:WU Zhen-ping  FU Fang-fa  XIAO Li-yi
Affiliation:(Microelectronics Center,Harbin Institute of Technology,Harbin 150001,China)
Abstract:A fault injection tool based on VHDL that implemented by simulator commands technique is proposed for supporting the sensitivity analysis of space processor.To demonstrate the tool,we use LEON3 processor as the target prototype to obtain the sensitivity of pipeline registers.Moreover,we harden the pipeline registers which are most sensitive and evaluate the reliability again.The fault injection tool presented by this paper can be also used to analyze sensitivity for other processor models by VHDL.
Keywords:fault injection  sensitivity analysis  simulator commands  VHDL
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