Motion estimation processor using mixed-signal approach

This paper describes the design, realization, and evaluation of a mixed-signal motion estimation processor using the full-search block-matching algorithm. The approach features digital I/O and a low-power, compact analog computational core. The proof-of-concept realization whose architecture incorporates pixel reuse, was fabricated in 0.8-/spl mu/m CMOS technology occupying 0.65 mm/sup 2/, and operates on 4 /spl times/ 4 pixel blocks and a search area of 8 /spl times/ 8 pixels. The processor achieves a low energy consumption per motion vector of 1.35 nJ and dissipates 0.8 mW from a 3-V power supply at QCIF 15 frames/s. The approach is intended for portable applications of digital video encoding.