Design and Evaluation of Adiabatic Arithmetic Units

Adiabatic design is an attractive approach to reducingenergy consumption in VLSI circuits after exhausting the potentialof conventional energy-saving techniques. Despite the plethoraof adiabatic logic architectures that have been proposed in recentyears, several practical considerations in the design of nontrivialadiabatic circuits remain largely unexplored. Moreover, it isstill unclear whether adiabatic circuits of significant sizeand complexity can achieve substantial savings in energy dissipationover corresponding conventional designs. We recently designedseveral low-power arithmetic units using a dual-rail adiabaticlogic design style. We also designed static CMOS versions ofthese units and compared their energy dissipation with theircorresponding adiabatic designs. In this paper we describe ourimplementations, discuss architecture and logic-level issuesrelated to our adiabatic designs, and present the findings ofour empirical comparison. Our results suggest that adiabaticlogic can be used for the implementation of relatively complexVLSI circuits that dissipate significantly less energy than theircorresponding CMOS designs.