Model-based mapping of reconfigurable image registration on FPGA platforms |
| |
| Authors: | Mainak Sen Yashwanth Hemaraj William Plishker Raj Shekhar Shuvra S. Bhattacharyya |
| |
| Affiliation: | (1) Department of Electrical and Computer Engineering, University of Maryland, College Park, MD, USA;(2) Institute for Advanced Computer Studies, University of Maryland, College Park, MD 20742, USA;(3) Department of Diagnostic Radiology, University of Maryland, Baltimore, MD 21201, USA;(4) Cisco Systems, San Jose, CA, USA;(5) Texas Instruments, Germantown, MD, USA |
| |
| Abstract: | Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficiency. This paper develops techniques for mapping rigid image registration applications onto configurable hardware under real-time performance constraints. Building on the framework of homogeneous parameterized dataflow, which provides an effective formal model of design and analysis of hardware and software for signal processing applications, we develop novel methods for representing and exploring the hardware design space when mapping image registration algorithms onto configurable hardware. Our techniques result in an efficient framework for trading off performance and configurable hardware resource usage based on the constraints of a given application. Based on trends that we have observed when applying these techniques, we also present a novel architecture that enables dynamically-reconfigurable image registration. This proposed architecture has the ability to tune its parallel processing structure adaptively based on relevant characteristics of the input images. |
| |
| Keywords: | Dataflow HPDF Image registration Reconfigurable architectures |
| 本文献已被 SpringerLink 等数据库收录！ |
|
