Dynamic noise model and its application to high speed circuit design |
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Authors: | Seung Hoon Choi Dinesh Somasekhar Kaushik Roy |
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Affiliation: | School of Electrical and Computer Engineering, Purdue University, 47907-1285 W. Lafayette, IN, USA |
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Abstract: | A dynamic noise model is developed and applied to analyze the noise immunities of precharge-evaluate circuits. With cross-talk being the main source of noise injection in the circuit, a simple metric represented as voltage-time product can be used to quantify the dynamic noise-margin. This is verified through HSPICE simulation on DOMINO gates. Based on this dynamic noise model, a tool is developed and applied to find the static and dynamic noise-margins at various points in the circuit with the effects of charge share and power/ground bounce taken into account. Obtained noise-margins are translated into maximum allowable coupling capacitances between the nodes for different types of precharge-evaluate logic circuits. The results show the difference in dynamic noise immunities in different logic families. Accurate estimates of dynamic noise-margins and coupling capacitance bounds will help design robust CMOS circuits. |
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Keywords: | Noise analysis Modeling Crosstalk Capacitance Simulation |
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