Phase-locked loop with dual phase frequency detectors for high-frequency operation and fast acquisition |
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Authors: | Youngshin WooYoung Min Jang Man Young Sung |
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Affiliation: | Semiconductor and CAD Laboratory, Department of Electrical Engineering, Korea University, 1, 5-ka, Anam-dong, Sungbuk-ku, Seoul 136-701, South Korea |
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Abstract: | The sequential phase frequency detector (PFD) has an unlimited error detection range and the precharge PFD has one and a half times better resolution performance than the sequential PFD. Therefore, by selective operation of the appropriate PFD connected to the well-adjusted charge pump, an unlimited error detection range, a high-frequency operation, and a higher speed lock-up time can be achieved. In this paper, we propose a phase-locked loop (PLL) with dual PFDs in which advantages of both PFDs can be combined. This structure can improve the tradeoff between acquisition behavior and locked behavior. |
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Keywords: | Dual phase frequency detectors Phase-locked loop High frequency Fast acquisition Low jitter CMOS |
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