| 基于FPGA的高速数据采集系统的设计与实现 |
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| 引用本文： | 常高嘉,冯全源.基于FPGA的高速数据采集系统的设计与实现[J].电子器件,2012,35(5):615-618. |
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| 作者姓名： | 常高嘉 冯全源 |
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| 作者单位： | 西南交通大学微电子研究所 |
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| 基金项目： | 国家自然科学基金项目(60990320,60990323);国家自然科学基金面上项目(61271090);国家高技术研究发展计划(863计划)项目(2012AA012305) |
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| 摘 要： | 高速数据采集系统主要由AD、FPGA和DSP组成。该系统的采样精度为12 bit,采样率为100 MSPS。首先介绍了系统中AD部分的两种前端调理电路的设计与实现,并作了对比,然后介绍了AD的时钟电路,说明了基于Verilog的FPGA程序设计过程。通过调试优化后可以在DSP中稳定、纹波较小地读到AD量化后的数据。
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| 关 键 词： | 数据采样系统 高速 前端调理电路 FPGA |
Design of High Speed Data Acquisition System based on FPGA |
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| CHANG Gaojia,FENG Quanyuan.Design of High Speed Data Acquisition System based on FPGA[J].Journal of Electron Devices,2012,35(5):615-618. |
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| Authors: | CHANG Gaojia FENG Quanyuan |
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| Affiliation: | (Institute of Microelectronics Southwest Jiaotong University,Chengdu 610031,China) |
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| Abstract: | This paper designed a high-speed data acquisition system consisting of AD,FPGA and DSP.The sampling accuracy is 12 bit,and sampling rate is 100 MSPS.This paper described two kinds of the front-end conditioning circuits and made a comparison between them,also described the clocking circuit of ADC,then introduced the design process of FPGA ’ s programs based on verilog.After debugging and optimizing,the wave which reads in the DSP is stable and with a low ripple. |
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| Keywords: | data acquisition system hight-speed front-end conditioning circuits FPGA |
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