Graph theory for FPGA minimum configurations |
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| Authors: | Ruan Aiwu Li Wenchang Xiang Chuanyin Song Jiangmin Kang Shi Liao Yongbo |
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| Affiliation: | State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China |
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| Abstract: | A traditional bottom-up modeling method for minimum configuration numbers is adopted for the study of FPGA minimum configurations.This method is limited if a large number of LUTs and multiplexers are presented. Since graph theory has been extensively applied to circuit analysis and test,this paper focuses on the modeling FPGA configurations.In our study,an internal logic block and interconnections of an FPGA are considered as a vertex and an edge connecting two vertices in the graph,respectively.A top-down ... |
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| Keywords: | graph theory minimum configuration number FPGA CLB IOB |
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