| An ultra high-speed 8-bit timing interleave folding＆interpolating analog-to-digital converter with digital foreground calibration technology |
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| 引用本文： | 张正平,王永禄,黄兴发,沈晓峰,朱璨,张磊,余金山,张瑞涛.An ultra high-speed 8-bit timing interleave folding＆interpolating analog-to-digital converter with digital foreground calibration technology[J].半导体学报,2011,32(9):133-139. |
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| 作者姓名： | 张正平 王永禄 黄兴发 沈晓峰 朱璨 张磊 余金山 张瑞涛 |
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| 作者单位： | No.24 Research Institute;China Electronics Technology Group Corporation;Science and Technology on Analog Integrated Circuit Laboratory; |
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| 摘 要： | A 2-Gsample/s 8-b analog-to-digital converter in 0.35μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 GSPS.Digital calibration technology is used for the offset and gain corrections of the S/H circuit,the offset correction of preamplifier,and the gain and clock phase corrections between channels.As a result of testing,the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected.
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| 关 键 词： | ultra high-speed interpolation algorithm folding analog-to-digital converter |
An ultra high-speed 8-bit timing interleave folding & interpolating analog-to-digital converter with digital foreground calibration technology |
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| Zhang Zhengping,Wang Yonglu,Huang Xingfa,Shen Xiaofeng,Zhu Can,Zhang Lei,Yu Jinshan,Zhang Ruitao.An ultra high-speed 8-bit timing interleave folding & interpolating analog-to-digital converter with digital foreground calibration technology[J].Chinese Journal of Semiconductors,2011,32(9):133-139. |
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| Authors: | Zhang Zhengping Wang Yonglu Huang Xingfa Shen Xiaofeng Zhu Can Zhang Lei Yu Jinshan Zhang Ruitao |
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| Affiliation: | 1. No.24 Research Institute, China Electronics Technology Group Corporation, Chongqing 400060, China
2. Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, China |
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| Abstract: | A 2-Gsample/s 8-b analog-to-digital converter in 0.35μm BiCMOS process technology is presented.The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 GSPS.Digital calibration technology is used for the offset and gain corrections of the S/H circuit,the offset correction of preamplifier,and the gain and clock phase corrections between channels.As a result of testing,the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected. |
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| Keywords: | ultra high-speed interpolation algorithm folding analog-to-digital converter |
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