A 0.13μm CMOS Δ ∑ fractional-N frequency synthesizer for WLAN transceivers |
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引用本文: | 楚晓杰,贾海珑,林敏,石寅,代伐.A 0.13μm CMOS Δ ∑ fractional-N frequency synthesizer for WLAN transceivers[J].半导体学报,2011(10):113-119. |
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作者姓名: | 楚晓杰 贾海珑 林敏 石寅 代伐 |
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作者单位: | Institute of Semiconductors;Chinese Academy of Sciences;Department of Electrical and Computer Engineering;Auburn University; |
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摘 要: | A fractional-N frequency synthesizer fabricated in a 0.13μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network(WLAN) transceivers.A monolithic LC voltage controlled oscillator(VCO) is implemented with an on-chip symmetric inductor.The fractional-TV frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping(MASH)△Σmodulator with noise-shaped dithering techniques.Measurement results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz.The integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm~2.
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关 键 词: | WLAN IEEE 802.11 b/g frequency synthesizer voltage controlled oscillator △∑modulator |
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