A 750 MHz semi-digital clock and data recovery circuit with 10~(-12) BER

A semi-digital clock and data recovery(CDR)is presented.In order to lower CDR trace jitter and decrease loop latency,an average-based phase detection algorithm is adopted and realized with a novel circuit.Implemented in a 0.13 μm standard 1P8M CMOS process,our CDR is integrated into a high speed serial and de-serial(SERDES)chip.Measurement results of the chip show that the CDR can trace the phase of the input data well and the RMS jitter of the recovery clock in the observation pin is 122 ps at 75 MHz clock frequency,while the bit error rate of the recovery data is less than 10 × 10-12.