基于FPGA的CRC编码器的实现

在数据通信中为了降低通信线路传输的误码率,需要采用高效能的差错控制方法,循环冗余校验CRC（Cyclic Redundancy Check）由于编码简单且有效,是一种最常用的信道编码方法.介绍了CRC编码的原理算法和校验规则,以CRC-4为例,给出了CRC校验码的具体计算过程和使用硬件描述语言VHDL来实现CRC编码的流程图,在程序中实现的是串行移位计算,并以Altera公司开发的EDA工具QuartusⅡ作为编译、仿真平台,选用Cyclone系列中的EP1C6T144C6器件,完成了CRC编码器的FPGA实现,其实现速度可达397 MHz.

Implementation of CRC Based on FPGA

In data communications,a high efficient error control method is needed to decrease the rate of error codes through transmission lines.CRC(Cyclic Redundancy Check)is a widely used channel coding method for its simple coding and high efficiency.The theory,algorithm and check regulations of CRC are introduced.Taking CRC4 as an example,the computation procedure and flow chart in VHDL of CRC are given.In the VHDL program,the computation is serial shift.QuartusII,an EDA tool developed by the Altera Company is used as the compilation and simulation platform.An EP1C6T144C6 belong to Cyclone is chosen to finish the FPGA realization.The realization speed is as high as 397 MHz.