| 时延约束的冗余通孔插入方法 |
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| 引用本文： | 王俊平,许丹,苏永邦. 时延约束的冗余通孔插入方法[J]. 半导体学报, 2014, 35(4): 045010-5 |
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| 作者姓名： | 王俊平 许丹 苏永邦 |
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| 作者单位： | [1]School of Telecommunications Engineering, Xidian University, Xi＇an 710071, China [2]School of Microelectronics, Xidian University, Xi＇an 710071, China |
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| 基金项目： | 基于随机缺陷的版图布线优化算法研究 |
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| 摘 要： | Redundant via （RV） insertion is a useful mechanism to enhance via reliability. However, when extra vias are inserted into the design, the circuit timing might be changed. Therefore, how to insert RV under the timing constraints is the main challenge. In this paper, we introduce a new model to compute the distance between a RV and the corresponding single via, put forward a new RV type, which is called the long length via （LLV）, and then present an improved RV insertion method considering the timing constraints. This computing model can certify that the timing, which is obtained aider inserting a RV, is not greater than the original timing. Meanwhile, the new RV type LLV can increase the possibility of RV insertion; this method provides a global perspective for the RV insertion. Considering the timing constraints, the total redundant via insertion rate is 85.38% in the MIS-based method, while our proposed method can obtain a high insertion rate 88.79% for the tested circuits.
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| 关 键 词： | 冗余 计时方法 计算模型 管理信息系统 时序约束 测试电路 插入方法 RV |
A method for timing constrained redundant via insertion |
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| Wang Junping,Xu Dan and Su Yongbang. A method for timing constrained redundant via insertion[J]. Chinese Journal of Semiconductors, 2014, 35(4): 045010-5 |
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| Authors: | Wang Junping Xu Dan Su Yongbang |
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| Affiliation: | School of Telecommunications Engineering, Xidian University, Xi'an 710071, China;School of Microelectronics, Xidian University, Xi'an 710071, China;School of Telecommunications Engineering, Xidian University, Xi'an 710071, China;School of Microelectronics, Xidian University, Xi'an 710071, China |
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| Abstract: | Redundant via (RV) insertion is a useful mechanism to enhance via reliability. However, when extra vias are inserted into the design, the circuit timing might be changed. Therefore, how to insert RV under the timing constraints is the main challenge. In this paper, we introduce a new model to compute the distance between a RV and the corresponding single via, put forward a new RV type, which is called the long length via (LLV), and then present an improved RV insertion method considering the timing constraints. This computing model can certify that the timing, which is obtained after inserting a RV, is not greater than the original timing. Meanwhile, the new RV type LLV can increase the possibility of RV insertion; this method provides a global perspective for the RV insertion. Considering the timing constraints, the total redundant via insertion rate is 85.38% in the MIS-based method, while our proposed method can obtain a high insertion rate 88.79% for the tested circuits. |
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| Keywords: | redundant via timing constraints integrated circuit |
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