| 基于FPGA的串行维特比译码的实现 |
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| 引用本文： | 陈春霞,王匡. 基于FPGA的串行维特比译码的实现[J]. 计算机工程, 2003, 29(14): 169-171 |
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| 作者姓名： | 陈春霞 王匡 |
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| 作者单位： | 浙江大学信电系,杭州,310027 |
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| 摘 要： | 维特比算法是一种卷积码译码算法。随着卷积码约束度的增加，并行维特比译码所需的硬件资源呈指数增长，限制其硬件实现。该文讨论了一种申行译码结构的FPGA实现方案。这种申行结构适合长约束度的卷积码译码，能在性能不下降的前提下有效地节省资源。
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| 关 键 词： | 卷积码 约束度 申行维特比译码 FPGA |
| 文章编号： | 1000-3428(2003)14-0169-03 |
| 修稿时间： | 2002-07-31 |
Implementation of Serial Viterbi Decoding Based on FPGA |
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| CHEN Chunxia,WANG Kuang. Implementation of Serial Viterbi Decoding Based on FPGA[J]. Computer Engineering, 2003, 29(14): 169-171 |
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| Authors: | CHEN Chunxia WANG Kuang |
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| Abstract: | Viterbi algorithm is applicable to decoding of convolutional codes. The hardware consumption of parallel Viterbi decoding shows exponential increase with the increase of constraint length of convolutional codes, which limits its hardware implementation. In this paper, the FPGA implementation of a serial Viterbi decoding architecture is presented. Suitable for decoding convolutional codes with long constraint length, this architecture saves hardware resource without performance deterioration. |
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| Keywords: | Convolutional codes Constraint length Serial viterbi decoding FPGA |
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