Estimation and compensation of process-induced variations in capacitors for improved reliability in integrated circuits

This paper describes a method for the estimation of capacitor process variations in integrated circuits and for the subsequent compensation of such variations through a calibration scheme that exploits a variable capacitor bank. An architecture for the calibration circuit is proposed, and various problems that arise during implementation are discussed. The design consists of an oscillator whose output frequency is inversely proportional to the capacitor value and simple state machine for measurement of capacitor process variations. The design of optimum capacitor bank is described together with the adequate tuning plan. The circuit is fabricated and verified in 130 nm RF CMOS process and can be easily scaled to sub-100-nm technologies.