A wideband calibration-free 1.5-GS/s 8-bit analog-to-digital converter with low latency |
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Authors: | Fan Jiang Danyu Wu Lei Zhou Yinkun Huang Jin Wu Zhi Jin Xinyu Liu |
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Affiliation: | 1. Institution of Microelectronics, Chinese Academy of Sciences, Beijing, 100029, China
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Abstract: | This article presents a wideband calibration-free 8-bit analog-to-digital converter (ADC) with low latency. The ADC employs a two-stage cascaded folding and interpolating architecture. A high-linearity and wideband track-and-hold amplifier combined with a low-parasitic-capacitance folding amplifier is employed to improve the performance. A binary-ROM with “keep-alive” current is proposed to guarantee no miscode when large bit-rate is input. When the sampling frequency is 1.5 GHz, the ADC achieves +0.29/?0.20 LSB DNL and 0.90 LSB INL. The ADC’s effective-number-of-bit and spur-free-dynamic-range are 7.0 bit and 51.8 dB respectively at 230 MHz input. The effective-resolution-bandwidth exceeds the second Nyquist zone up to 1.8 GHz. All of this makes this ADC suitable for wideband digital receiver system. |
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