0.1-μm p+-GaAs gate HJFET's fabricated using two-stepdry-etching and selective MOMBE growth techniques

This paper reports the first successful fabrication of high-performance, 0.1-μm p⁺-gate pseudomorphic heterojunction-FET's (HJFET's). By introducing the two-step dry-etching technique which compensates for the poor dry-etching resistance of PMMA, 0.1-μm or less gate-openings with a high aspect-ratio of 3.5 in SiO ₂ film are achieved. In addition, by using the gate electrode filling technique with selective MOMBE p⁺-GaAs growth, 0.1-μm voidless p⁺-GaAs gate electrodes with a high aspect-ratio are achieved for the first time. The fabrication technology leads to a reduction of external gate fringing capacitance (Ce^ext _f) in a T-shaped gate-structure and an improvement in gate turn-on voltage. The fabricated 0.1-μm, T-shaped, p⁺-gate n-Al_0.2Ga_0.8As/In_0.25Ga_0.75 As HJFET exhibits a high gate turn-on voltage (V_f) of about 0.9 V, and a good gm_max of 435 mS/mm. Also, an excellent microwave performance of f_T=121 GHz and f_max =144 GHz is achieved due to the C^ext_f reduction. The technology and device show great promise for future high-speed applications, such as in power devices, MMIC's, and digital IC's