Heat transfer analysis on wafer annealing process in semiconductor multi-wafer furnace using CFD simulation

This study employs a three-dimensional numerical model to simulate a vertical furnace for wafer annealing process. For a conventional furnace design, it is revealed that the top 5 pieces of the stacked wafers are exposed to lower temperatures, approximately 3–5 % lower than the operating heater temperature. Temperature distribution and the heat losses from the furnace, especially on the heat dissipated through the top header and the process door of the furnace chamber, are examined. To reduce the heat losses, furnace design improvements comprised of a thicker top header and a better thermal insulated process door are recommended. With such implementations, up to 28 % and 22 % reduction of heat dissipation through the top header and the process door, respectively, could be attained. In addition, the design of the boat cover is found to influence the temperature uniformity across the stacked wafers. To attain better temperature uniformity at the top region of stacked wafers, a furnace with a full boat cover is thus recommended.