| 基于FPGA的4k点基-16FFT模块的实现 |
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| 引用本文： | 苏彦鹏,张汉富,韩磊. 基于FPGA的4k点基-16FFT模块的实现[J]. 电子与封装, 2007, 7(9): 8-11 |
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| 作者姓名： | 苏彦鹏 张汉富 韩磊 |
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| 作者单位： | 江南大学信息工程学院,江苏,无锡,214122;中电集团公司第58研究所,江苏,无锡,214035 |
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| 摘 要： | 针对高速实时处理的要求,提出了4096点快速傅立叶变换(FFT)模块在现场可编程门阵列(FPGA)中的设计和实现。在运算模块中,基于按频率抽取基-4算法提出了一种新型的基-16蝶型算法,并采用八级流水结构和四路转换器来实现。本文采用块浮点和循环存储结构,避免了溢出和节省了大量的硬件资源。实验结果表明,该方法在保证了运算精度和实现复杂度的同时,使运算速度相对于基-4算法提高了1倍。
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| 关 键 词： | 快速傅立叶变换 基-16算法 现场可编程门阵列 |
| 文章编号： | 1681-1070（2007）09-0008-04 |
| 修稿时间： | 2007-01-16 |
Implementation of the 4k Point Radix-16 FFT Module Based on FPGA |
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| SU Yan-peng,ZHANG Han-fu,HAN Lei. Implementation of the 4k Point Radix-16 FFT Module Based on FPGA[J]. Electronics & Packaging, 2007, 7(9): 8-11 |
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| Authors: | SU Yan-peng ZHANG Han-fu HAN Lei |
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| Affiliation: | 1. School of Information Engineering Southern Yangtze University, Wuxi 214122, China; 2. The 58th Institute of China Electronics Group Corp., Wuxi 214035, China |
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| Abstract: | According to the need of high-speed processing for real-time, the design and implementation of 4096 point fast fourier transform module in field programmable gate array is presented. In operation module, based on decimate in frequency radix-4 algorithm, a new radix-16 butterfly algorithm is discussed, which is implemented by 8 levels pipeline structure and 4-input multiplexer. The adopt of block-floating-point avoid overflow and cycle storage structure save much hardware resource. Experimental results show that this method performs good accuracy and complication, and moreover can double the speed compared with radix-4 algorithm. |
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| Keywords: | fast fourier transform radix-16 algorithm field programmable gate array |
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