Noise estimation for deep sub-micron integrated circuits

Noise analysis and avoidance are an increasingly critical step in the design of deep sub-micron (DSM) integrated circuits (ICs). The crosstalk between neighboring interconnects gradually becomes the main noise sources in DSM ICs. We introduce an efficient and accurate noise-evaluation method for capacitively coupled nets of ICs. The method holds for a victim net with arbitrary number of aggressive nets under ramp input excitation. For common RC nets extracted by electronic design au-tomation (EDA) tools, the deviation between our method and HSPICE is under 10% .