高速数据采集系统中时钟的设计

本文介绍在采用分相多路数字化技术的高速数据采集系统中,等相位差同频率时钟的的设计重点.讨论高频系统中时钟参数对系统性能的影响,提出利用FPGA内部的锁相环PLL产生时钟信号的设计方案,消除时钟抖动、减小相位噪声.文中给出数据采集系统的一种时钟设计实例,并对设计方案进行仿真分析,可以应用于最高实时采样率800MHz数据采集系统中.

Clock design in high speed data acquisition

The design keys of clocks with equal phase difference and frequency is introduced in the paper which is used in the data acquisition system adopts multiplex digitalize technique. After discussing the timing parameters influence the system performance, a proposal of using the internal PLL in FPGA to generate the clock signals is put forward. It does well in eliminating the clock jitter and the phase noise. The clock design instance of data acquisition is described in this paper, the emulation as well as analysis is present. The design is applied in the data acquisition system of 800MHz real-time sample rate.