基于ILP的电压岛驱动的多电压分配算法

为降低芯片功耗和电源布线网络的复杂度，针对可切分的布图结构，提出了一种时序约束下在后布图阶段进行多电压分配的整数线性规划模型，对功耗和电源网络进行协同优化，同时控制插入电平移位器的数目。为构建电源网络复杂度的度量模型，提出了一种时间复杂度仅为[O(n)]的模块相邻图构建方法来获得模块之间的相邻信息。模型中还考虑了在不同电压差的模块之间连线上插入不同延时和功耗的电平移位器，以进一步降低功耗。对5个GSRC电路的实验结果表明：所提出算法不仅可降低16.7~31.5%不等的功耗，还可将相同电压的模块有效集中在一起，形成电压岛。

ILP-based voltage island-driven multiple voltage assignment algorithm

To reduce chip’s power consumption and power networks complexity for slicing floorplan, an ILP（Integer Linear Programming）formulation is proposed to handle the Multiple Voltage Assignment（MVA） problems under timing constraints at post-floorplanning stage, collaboratively optimizing the power consumption and power networks, and controlling the number of inserted level shifters. To model the power network complexity, a fast construction method of Block Adjacency Graph（BAG） is proposed to obtain blocks’ adjacency in the floorplan and its time complexity is only [O(n)]. Those nets with different voltage gap between blocks are considered to insert level shifters with different delay and power consumption. Experimental results on five GSRC circuits show that the proposed algorithm not only can reduce the power consumption of 16.7%~31.5%, but also can effectively cluster blocks with the same voltage to generate voltage islands.