A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology |
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引用本文: | 乔宁,张国全,杨波,刘忠立,于芳.A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology[J].半导体学报,2012,33(9):115-123. |
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作者姓名: | 乔宁 张国全 杨波 刘忠立 于芳 |
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作者单位: | Institute of Semiconductors,Chinese Academy of Sciences,Beijing 100083,China;Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China |
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摘 要: | 正A 10-bit 50-MS/s reference-free low power successive approximation register(SAR) analog-to-digital converter(ADC) is presented.An energy efficient switching scheme is utilized in this design to obtain low power and high frequency operation performance without an additional analog power supply or on-chip/off-chip reference. An on-chip calibration DAC(CDAC) is implemented to cancel the offset of the latch-type sense amplifier(SA) to ensure precision whilst getting rid of the dependence on the pre-amplifier,so that the power consumption can be reduced further.The design was fabricated in IBM 0.18-μm 1P4M SOI CMOS process technology.At a 1.5-V supply and 50-MS/s with 5-MHz input,the ADC achieves an SNDR of 56.76 dB and consumes 1.72 mW,resulting in a figure of merit(FOM) of 61.1 fJ/conversion-step.
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关 键 词: | successive approximation register analog-to-digital converter reference-free on-chip calibration energy efficient |
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