Low power fast settling multi-standard current reusing CMOS fractional-N frequency synthesizer |
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Authors: | Lou Wenfeng Feng Peng Wang Haiyong Wu Nanjian |
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Affiliation: | State Key Laboratory for Superlattices and Microstructures,Institute of Semiconductors,Chinese Academy of Sciences, Beijing 100083,China |
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Abstract: | A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed.The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer.An auxiliary non-volatile memory(NVM) is embedded to avoid the repetitive calibration process and to save power in practical application.This PLL is implemented in a 0.18μm technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5μs over the entire frequency range.The LC-VCO with the stacked divide-by-2 has a good figure of merit of-193.5 dBc/Hz.The measured phase noise of frequency synthesizer is about-115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than -52 dBc.The whole frequency synthesizer consumes only 4.35 mA @ 1.8 V. |
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Keywords: | phase-locked loop current reusing forward-body bias divide-by-2 multi-standard fast settling |
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