| 用于SVC数控系统的数字锁相环的设计与实现 |
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| 引用本文： | 张志文,郭斌,罗隆福,曾志兵,王伟. 用于SVC数控系统的数字锁相环的设计与实现[J]. 电力系统及其自动化学报, 2011, 23(1): 103-107 |
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| 作者姓名： | 张志文 郭斌 罗隆福 曾志兵 王伟 |
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| 作者单位： | 湖南大学电气与信息工程学院,长沙,410082 |
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| 摘 要： | 为减少在静止无功补偿(SVC)装置中晶闸管的触发误差,设计了一种基于FPGA(现场可编程门阵列)的全数字锁相环(ADPLL),并进行硬件电路测试.同时分析了全数字锁相环的各模块工作原理并进行了参数设计和电路仿真.最后在实验平台上进行了测试.结果显示,该环路可稳定跟踪电网信号,可为SVC数字控制系统提供快速、稳定、高精度...
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| 关 键 词： | 全数字锁相环 静止无功补偿装置 触发误差 现场可编程门阵列 同步信号 |
Design and Realization of Digital Phase Locked Loop for Control System of SVC |
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| ZHANG Zhi-wen,GUO Bin,LUO Long-fu,ZENG Zhi-bing,WANG Wei. Design and Realization of Digital Phase Locked Loop for Control System of SVC[J]. Proceedings of the CSU-EPSA, 2011, 23(1): 103-107 |
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| Authors: | ZHANG Zhi-wen GUO Bin LUO Long-fu ZENG Zhi-bing WANG Wei |
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| Affiliation: | ZHANG Zhi-wen,GUO Bin,LUO Long-fu,ZENG Zhi-bing,WANG Wei(College of Electrical and Information Engineering,Hunan University,Changsha 410082,China) |
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| Abstract: | In order to reduce the thyristor triggering error in the static var compensator(SVC),all digital phase-locked loop(ADPLL) is designed based on field programmable gate array(FPGA).Principle of each module is analyzed,and the parameter design and the circuit simulation are completed.Finally,it is tested on experimental platform.The result shows that the ADPLL can stably track power network signal.It provides fast,stable and accurate synchronized signal for the SVC numerical control system. |
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| Keywords: | all digital phase locked loop(ADPLL) static var compensator(SVC) triggering error field programmable gate array(FPGA) synchronized signal |
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