一种新颖的乘法器核内建自测试设计方法

提出一种新颖的乘法器核内建自测试（BIST）方法。结合C可测性与伪随机测试的优点。所设计的测试电路的附加面积比传统的伪随机电路要低56％，该方法采用独特的赋值方法。生成精简的、故障覆盖率高于99％的测试图形，并用开发的软件对测试图形排序和压缩，平均跳变密度和宽度得以大大减少．基于上述研究成果，可容易实现低成本BIST电路，基于Synopsys相关工具软件的模拟和分析结果表明，提出的BIST电路在面积、功耗和速度等方面均优于现有的BIST设计。

A novel BIST technique for multipliers cores

A novel built-in self-test(BIST) scheme for multiplier cores is proposed.The scheme combines the advantages of C-testable and pseudorandom testing,and the designed test circuit imposes small extra hardware,which is less than that of the pseudorandom testing circuit by 56%.In test generation,the proposed method uses the unique assigning technique to achieve a very small test set with fault coverage higher than 99%.The generated test set is reordered and compressed by our developed program,and its switching activities and width are drastically reduced.Based on the above results,a low cost circuit can be easily implemented.Experimental results show that the designed BIST circuits are superior to other BIST circuits in hardware,power consumption and test time.