Optimization of printed circuit board interconnectivity testing for parallel devices |
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Authors: | Jeonghoon Mo |
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Affiliation: | Department of Information and Industrial Engineering, Yonsei University, Seoul, Korea |
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Abstract: | In this article, the problems of test sequence generation and scheduling optimization for a tester with parallel devices are considered in order to reduce inspection times. Two optimization problems are formulated for test sequence generation and the scheduling of parallel devices, and then algorithms to address these problems are proposed. The proposed algorithms were tested via simulation and experiments. The test results show two to four times improvement over existing methods. |
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Keywords: | Printed circuit board test sequence open test integer programming |
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