IC设计中的ESD保护技术探讨

ESD是集成电路设计中最重要的可靠性问题之一。IC失效中约有40%与ESD/EOS(电学应力)失效有关。为了设计出高可靠性的IC,解决ESD问题是非常必要的。文中讲述一款芯片ESD版图设计,并且在0.35μm 1P3M 5V CMOS工艺中验证,成功通过HBM-3000V和MM-300V测试。这款芯片的端口可以被分成输入端口、输出端口、电源和地。为了达到人体放电模型(HBM)-3000V和机器放电模型(MM)-300V,首先要设计一个好的ESD保护网络。解决办法是先让ESD的电荷从端口流向电源或地,然后从电源或地流向其他端口。其次,给每种端口设计好的ESD保护电路,最后完成一张ESD保护电路版图。

ESD Protection Issues in IC Design

Electrostatic discharge(ESD) is one of the most important reliability issues in the integrated circuit(IC) industry,and nearly 40% of all IC failures are associated with ESD/EOS(electrical overstress) related modes.Therefore,controlling ESD is indispensable for achieving higher quality and reliability standards of IC chips.This paper presents ESD circuit and layout design of a chip.The chip is verified in 0.35μm 1P3M 5V cmos process and has passed HBM-3000V MM-300V ESD test.The chip’s ports can be divided into four categories: input port,output port,vdd and vss ports,open-drain output port.For achieving the goal of HBM3000V and MM-300V,a good ESD protection network must be selected firstly.The ESD solution relies on shunting charge from an I/O pin to a power supply,from which the charge can be distributed to other I/O pins.Secondly,good ESD protection circuit and devices are designed.At last,designing a good ESD protection layout is important.