| SOPC技术在计算全息中的应用 |
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| 引用本文： | 郁伟勇,简献忠,奚利丰,郭强,於江赟.SOPC技术在计算全息中的应用[J].计算机系统应用,2013,22(7):40-44. |
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| 作者姓名： | 郁伟勇 简献忠 奚利丰 郭强 於江赟 |
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| 作者单位： | 上海理工大学 光电信息与计算机工程学院, 上海 200093;上海理工大学 光电信息与计算机工程学院, 上海 200093;上海理工大学 光电信息与计算机工程学院, 上海 200093;国家卫星气象中心, 北京 100081;上海理工大学 光电信息与计算机工程学院, 上海 200093 |
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| 基金项目： | 上海市研究生创新基金(JWCXSL1102);国家自然科学基金(40971200) |
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| 摘 要： | 基于计算全息术的三维动态实时显示受到越来越多的关注, 而制约其发展的一大难题是其运算速度. 针对这一问题, 本文提出基于SOPC(System On Programmable Chips)技术的计算全息硬件加速系统, 使多片FPGA硬件进行分块并行运算. 为了实现这一目标, 每片FPGA运算单元必须独立具备数据传输与计算全息算法加速两种功能. 在已有计算全息算法加速模块的基础上, 搭载NIOS II软核并移植uC/OS II操作系统及LWIP以太网协议栈. NIOS II软核作为FPGA的主控, 控制计算全息算法加速模块及以太网口的数据传输, 实验结果证明该方法为实现计算全息三维动态实时显示提供了一种新的思路.
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| 关 键 词： | 计算全息 以太网 FPGA NIOS II软核 uC/OS II LWIP |
| 收稿时间： | 2012/12/10 0:00:00 |
| 修稿时间： | 2013/1/11 0:00:00 |
Calculation of the Holography Based on SOPC Technology |
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| YU Wei-Yong,JIAN Xian-Zhong,XI Li-Feng,GUO Qiang and YU Jiang-Yun.Calculation of the Holography Based on SOPC Technology[J].Computer Systems& Applications,2013,22(7):40-44. |
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| Authors: | YU Wei-Yong JIAN Xian-Zhong XI Li-Feng GUO Qiang and YU Jiang-Yun |
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| Affiliation: | University of Shanghai for Science & Technology, Shanghai 200093, China;University of Shanghai for Science & Technology, Shanghai 200093, China;University of Shanghai for Science & Technology, Shanghai 200093, China;National Weather Satellite Center, Beijing 10081, China;University of Shanghai for Science & Technology, Shanghai 200093, China |
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| Abstract: | More and more people pay attention to real-time three-dimensional dynamic display technology based on computer generated hologram. The major problem to restrict its development is computing speed. To solve the problem, we build PC-FPGA distributed computing holographic hardware acceleration system that multi-chip FPGA hardware block computing paralleled. Each chip FPGA unit must have the functions both of holographic algorithms computing and the data transmission to achieve this goal. Therefore, NIOS II soft core transplant uC/OS II operating system and LWIP Ethernet protocol stack based on already CGH algorithm acceleration module, NIOS II as the MCU to control CGH algorithm acceleration module and Ethernet data transmission. The article will introduce the NIOS II soft-core, uC/OS II and LWIP achieve to Ethernet data transmission process. To provide a new method to the realization of three-dimensional dynamic real-time display based on CGH. |
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| Keywords: | CGH Ethernet FPGA NIOS II uC/OS II LWIP |
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