| 一种用于功率IC中高性能PNP管的版图设计 |
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| 引用本文： | 董艳燕. 一种用于功率IC中高性能PNP管的版图设计[J]. 中国计量学院学报, 2008, 19(1): 78-81 |
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| 作者姓名： | 董艳燕 |
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| 作者单位： | 中国计量学院,光学与电子科技学院,浙江,杭州,310018 |
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| 摘 要： | 在对传统横向PNP管版图和晶体管寄生效应分析的基础上,提出了一种基于双极工艺的横向PNP管设计方案,并给出了一个适用于功率集成电路中高性能横向PNP输出管的版图设计.
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| 关 键 词： | 功率集成电路 高性能PNP管 版图设计 |
| 文章编号： | 1004-1540(2008)01-0078-04 |
| 修稿时间： | 2007-12-29 |
A layout design of the high-performance PNP transistor in the power IC |
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| DONG Yan-yan. A layout design of the high-performance PNP transistor in the power IC[J]. Journal of China Jiliang University, 2008, 19(1): 78-81 |
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| Authors: | DONG Yan-yan |
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| Affiliation: | DONG Yan-yan ( College of Optical and Electronic Science and Technology, China Jiliang University, Hangzhou 310018, China) |
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| Abstract: | Based on an analysis of traditional long PNP transistor＇s layout and its parasitics, a design scheme of long PNP transistor by bipolar technology is proposed. The realization of the layout for high-performance LPNP transistors of power IC is offered. |
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| Keywords: | power IC high performance PNP transistor layout design |
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