Synchronous derived clock and synthesis of low power sequential circuits |
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Authors: | Xunwei Wu Wu Qing Pedram Massoud |
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Affiliation: | (1) Department of Electronic Engineering, Zhejiang University, 310028 Hangzhou;(2) Department of Electrical Engineering-Systems, University of Southern California, USA |
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Abstract: | Based on analyzing significance of controlling clock in design of low power sequential circuits, this paper proposes a technique that the gating signal is derived from the master latch in a flip-flop to make the derived clock having no glitch and no skew. The design of a decimal counter with half-frequency division shows that by using the synchronous derived clock the counter has lower power dissipation as well as simpler combinational logic. Computer simulation shows 20% power saving. |
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Keywords: | Low power Sequential circuit Logic design Derived clock |
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