JPEG2000中DWT-EBCOT联合的高效低存储VLSI结构

针对JPEG2000硬件实现中小波变换与编码之间占用大量存储的问题，该文提出一种基于码块的存储方案。通过对码块大小片内存储最大程度的复用以及对其高效简单的调度控制，从面积和功耗两方面减小了硬件实现的开销。在实现中，采用基于行的提升变换结构和比特平面并行的编码方式，提高了效率，确保整个过程的实时处理。实验结果表明:在实时编码要求下，对分辨率为512512的图像分片进行四级9/7或者5/3小波分解，码块大小为3232，采用本文结构所用的存储量与直接使用外部存储器的方法相比可减少80%以上。整个结构已通过FPGA验证，且系统时钟可以工作在100MHz。

An Efficient DWT-EBCOT Combined VLSI Architecture with Low Memory for JPEG2000

Motivated by an enormous amount of storage between DWT and EBCOT in JPEG2000 hardware implementation, a novel memory-efficient scheme based on code block size is proposed. Further reuse of on-chip code block size memories and efficient scheduling of them reduce hardware cost in both area and power. In the implementation, line-based lifting DWT architecture and bit plane parallel EBCOT design are used. The resulting coding efficiency is improved and the whole architecture can achieve real time processing. Experimental results show that on demand of real time coding, when a tile with resolution up to 512-width and 512-height is decomposed with four levels in 9/7 or 5/3 filters and the size of code block is 32×32, the wavelet coefficients memory needed in the proposed architecture is reduced by over 80%, compared with existing architectures that wavelet coefficients are directly deposited in off-chip memories. The whole design has been synthesized and mapped into Xilinx FPGA, passing the verification when the system is working at the clock of 100MHz.