| 基于FPGA的DDR SDRAM控制器设计与实现 |
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| 引用本文： | 高群福,陈星,程越.基于FPGA的DDR SDRAM控制器设计与实现[J].电子测量技术,2011,34(8):56-59. |
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| 作者姓名： | 高群福 陈星 程越 |
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| 作者单位： | 北京航空航天大学电子信息工程学院 北京100191 |
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| 摘 要： | 在高速数据采集系统中,高速大容量数据缓存成为1项关键技术.DDR SDRAM凭借其大容量、高数据传输速率和低成本优势,正在越来越多的被应用于高速数据采集系统中.采用Altera公司的Cyclone III系列FPGA和MT46V16M16 DDR SDRAM芯片作为硬件平台,完成了DDR SDRAM控制器的设计,使用S...
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| 关 键 词： | DDR SDRAM FPGA 控制器 状态机 FIFO 数据通路 |
Design and implementation of DDR SDRAM controller based on FPGA |
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| Gao Qunfu,Chen Xing,Cheng Yue.Design and implementation of DDR SDRAM controller based on FPGA[J].Electronic Measurement Technology,2011,34(8):56-59. |
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| Authors: | Gao Qunfu Chen Xing Cheng Yue |
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| Affiliation: | Gao Qunfu Chen Xing Cheng Yue(School of Electronic and Information Engineering,Beihang University,Beijing 100191) |
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| Abstract: | In high-speed data acquisition systems,high-speed and large-capacity data cache is becoming a key technology.DDR SDRAM,with its large capacity,high data transfer rate and low cost,are increasingly being used in high-speed data acquisition system.Altera's Cyclone III FPGA and MT46V16M16 DDR SDRAM chips as the hardware platform,complete the design of DDR SDRAM controller,using signal tap tool testing and verifying the DDR SDRAM controller on the hardware platform. |
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| Keywords: | DDR SDRAM FPGA controller state machine FIFO data path |
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