| Rijndael算法的硬件实现 |
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| 引用本文： | 刘向宇,曹秀英.Rijndael算法的硬件实现[J].通信技术,2002(8):75-77. |
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| 作者姓名： | 刘向宇 曹秀英 |
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| 作者单位： | 东南大学移动通信国家重点实验室,南京,210096 |
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| 基金项目： | 863高科技资助项目(编号2001AA140328)。 |
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| 摘 要： | 提出了Rijndael的硬件实现的算法,它是128位对称分组加密的高级加密标准。设计目标是FPGA实现。系统由AddroundKey、ShiftRows、Mixcolumns和s盒四个部分组成。因为Rijndael算法需要大量硬件资源,每一个部分除了S盒外都只实现了一次,并工作在非反馈模式下。该设计在MAX+PLUSIIFPGA工具中进行了仿真。
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| 关 键 词： | AES(高级加密标准) 对称分组加密 硬件 Rijndeal算法 |
| 修稿时间： | 2002年4月5日 |
Hardware Implementation of Rijndael Ciper Algorithm |
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| Liu Xiangyu Cao Xiuying.Hardware Implementation of Rijndael Ciper Algorithm[J].Communications Technology,2002(8):75-77. |
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| Authors: | Liu Xiangyu Cao Xiuying |
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| Abstract: | This paper presented a Hardware impl ementation of Rijndael,which isAdvanced Encrp-tion Standard 128-bit symmetric blo ck cipher.The target of the design wa s FPGA.And the system consists of AddroundKey part,ShiftRows part,Mixcolumns part and S -box part.Sin ce Rijndael algorithm requires a lot of hardware resources,each uni t was designed only once except S -box and operated in non -feed-back mode.The design was simulated i n MAX +_PLUS II FPGA tool. |
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| Keywords: | AES(Advanced Encrption Standard) symmetric block cipher hardware Rijndael algo-rithm |
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