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Metal Drain Double-Gate Tunnel Field Effect Transistor with Underlap: Design and Simulation |
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| Authors: | Khan Anam Loan Sajad A |
| Affiliation: | 1.Department of Electronics and Communication Engineering, Jamia Millia Islamia, New Delhi, 110025, India ; |
| Abstract: | Silicon - In this paper, we propose and simulate a novel double gate tunnel field effect transistor (DG-TFET) employing a metallic drain and a gate-drain underlap. The use of a metallic drain and... |
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