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Architecture- and Gate-Oxide-Level Optimization of a Si-Based Asymmetric U-TFET for Low Power Operation: a Real-Time Gate/Drain Electrostatic Based Leakage Perspective |
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| Authors: | Das Suman Chattopadhyay Avik Tewari Suchismita |
| Affiliation: | 1.Department of Electronics and Communication Engineering, Sikkim Manipal Institute of Technology, Sikkim Manipal University, East Sikkim, Sikkim, 737136, India ;2.Institute of Radio Physics and Electronics, University of Calcutta, Kolkata, West Bengal, 700009, India ; |
| Abstract: | Silicon - In this paper, for the first time, an optimized asymmetric U-shaped TFET, suitable for low power application, has been proposed after a hardcore performance analysis, considering the... |
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