一种用于H.264编解码的新型高效 可重构多变换VLSI结构

H.264/AVC标准采用了4×4整数变换.本文针对4×4正反变换分别提出了两个新的二维直接信号流图.在此基础上,设计了一个支持多变换的可重构高性能二维结构.该结构无需转置寄存器.采用0.18微米CMOS工艺实现了该电路结构.结果表明,该结构同现有典型结构相比具有更高的效率.同采用三个独立的单一变换结构实现的ASIC相比,可重构结构以较少的效率下降(14.4%)获得了较大的芯片面积节省(61.1%).在100MHz的时钟频率下工作,该电路即可实时处理分辨率为4096×2048、每秒60帧的高质量视频序列.

A High-Performance Reconfigurable Multi-Transform VLSI Architecture for H.264 CODEC

The 4×4 integer transforms are adopted in the H.264/AVC standard. In this paper,two novel 2-D direct signal flow graphs of the 4×4 forward and inverse transforms for H.264 are proposed.A high-performance reconfigurable 2-D architecture without using transpose memory for the multiple transforms is proposed on the basis of the new SFGs.Our design is implemented with 0.18um CMOS technology.The proposed design is more efficient than the existing typical designs.Compared with the ASIC realization having 3 single transform architectures,the reconfigurable architecture obtains a large scaled area reduction (61.1%) with only a small efficiency decrease (14.4%).Under a clock frequency of 100 Mhz,the architecture allows the real-time processing of 4096×2048 at 60fps.