Fully-Depleted SOI CMOS Technology for Low-Voltage Low-Power Mixed Digital/Analog/Microwave Circuits |
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| Authors: | D. Flandre J. P. Colinge J. Chen D. De Ceuster J. P. Eggermont L. Ferreira B. Gentinne P. G. A. Jespers A. Viviani R. Gillon J. P. Raskin A. Vander Vorst D. Vanhoenacker-Janvier F. Silveira |
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| Affiliation: | (1) Microelectronics Laboratory, Universite´ Catholique de Louvain, Place du Levant 3, 1348 Louvain-la-Neuve, Belgium;(2) Microwaves Laboratory, Universite´ Catholique de Louvain, Place du Levant 3, 1348 Louvain-la-Neuve, Belgium;(3) Instituto de Ingenierìa Ele`ctrica, Universidad de la Repu`blica, Casilla de Correos 30, Montevideo, Uruguay |
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| Abstract: | This paper demonstrates that fully-depleted (FD) silicon-on-insulator (SOI) technology offers unique opportunities in the field of low-voltage, low-power CMOS circuits. Beside the well-known reduction of parasitic capacitances due to dielectric isolation, FD SOI MOSFETs indeed exhibit near-ideal body factor, subthreshold slope and current drive. These assets are both theoretically and experimentally investigated. Original circuit studies then show how a basic FD SOI CMOS process allows for the mixed fabrication and operation under low supply voltage of analog, digital and microwave components with properties significantly superior to those obtained on bulk CMOS. Experimental circuit realizations support the analysis. |
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| Keywords: | SOI Technology CMOS circuits LVLP mixed-mode RF components |
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